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The present invention relates generally to SIMD array processors, and more specifically to SIMD array processors having improved data transfer efficiency between processing elements incorporated therein.
Single-Instruction Multiple-Data (SIMD) array processors are known which comprise multi-dimensional arrays of interconnected processing elements executing the same instruction simultaneously on a plurality of different data samples. For example, an SIMD array processor may include a two-dimensional array of processing elements in which each processing element is connected to its four (4) nearest neighboring processing elements to form a xe2x80x9cNorth, East, West, South (NEWS) arrayxe2x80x9d. In such NEWS arrays, each processing element can communicate directly with its North, East, West, and South neighbors.
One aspect of the typical SIMD array processor that limits the rate at which the processing elements can communicate with each other is that one or more of the neighboring processing elements with which a particular processing element communicates may be physically located on a different Application Specific Integrated Circuit (ASIC) and/or on a different Printed Circuit Board (PCB). For example, when a processing element directly accesses a multi-bit data sample from a neighboring processing element physically located on a different ASIC or a different PCB, a significant amount of time may be required for that data sample to propagate between the ASIC""s or PCB""s. To account for this propagation time, communication registers used in processing elements of the typical SIMD array processor are generally clocked at relatively low speeds. However, clocking communication registers at such low speeds may cause many operating cycles of a processing element to be wasted while the processing element waits for the data transfer to complete. As a result, the typical SIMD array processor may not be suitable for some high-speed data processing applications.
It would therefore be desirable to have an SIMD array processor that has improved data transfer efficiency between processing elements incorporated therein. Such an SIMD array processor would transfer data samples more efficiently whether or not neighboring processing elements are located on the same ASIC or PCB.
In accordance with the present invention, an SIMD array processor is provided in which data transfer efficiency is enhanced between processing elements included therein. The SIMD array processor includes a plurality of mesh-connected processing elements configured in a multi-dimensional array. Each processing element includes at least one xe2x80x9cnarrowxe2x80x9d memory buffer, at least one xe2x80x9cwidexe2x80x9d data register, and at least one xe2x80x9cwidexe2x80x9d communication register. The narrow memory buffer is adapted to transfer data serially between a memory and the wide data register; and, the wide data register is adapted to transfer data directly to the wide communication register. Further, the wide communication register is adapted to transfer data directly to the communication register of a neighboring processing element while the memory buffer accesses data from memory. In a preferred embodiment, the memory buffer has a width of one (1) bit to allow bit-serial data transfer between the memory and the wide data register while the wide communication register transfers data in parallel to (from) the communication register of the neighboring processing element.
Other features, functions, and aspects of the invention will be evident from the Detailed Description of the Invention that follows.